AF Vehicle blog — September 27, 2009
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Just a quick note to say I have successfully completed test #2.
Second inter-module communication test
As with the first test, this was simply a demonstration that the transmitting module could send data reliably to the receiver module. The transmitter was programmed to send hundreds of "bogus" packets, intersperced with two test packets that the receiver was to receive and store. The module select byte is what distinguished the good packets from the bogus ones.
Results
Anazingly, there was only one glitch, which was just a firmware bug not caught during simulation testing. Once corrected, the test worked flawlessly. The two packets were received and stored in EEPROM correctly (as noted above, they had to be stored in a RAM buffer temporarily, since the EEPROM writing is far too slow to keep up with the transmission rate).
This demonstrated that a one-wire bus is quite feasible, and I believe will have sufficient bandwidth for the purpose. It is quite probable that I can reduce the timing of some of the pulses and still maintain reliability. For instance, I currently have a "0" bit at 20 µS, which seems to be the practical mininum, but a "1" bit at 50 µS. I could probably reduce this to 40 or even 30 µS. Other timings could probably be reduced accordingly.
I realize this is hardly earth-shattering, but for me it is the first time I have attempted to get these controllers to talk to each other, and it is gratifying that it seems to be fairly straightforward, and reliable. It also shows that the "break" serves as a good way to synchronize and to indicate the start of a new packet. This means that the receiver, which may well be doing other processing, can pretty much come in anywhere in the sequence and pick up the required packet.
AF Vehicle blog — September 27, 2009
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